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PRELIMINARY
CY7C9689
TAXITM Compatible HOTLinkTM Transceiver
Features
* * * * * * * * * * * * * * Second-generation HOTLinkTM technology AMDTM AM7968/7969 TAXIchipTM compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded (bypass) data transport Synchronous TTL parallel interface Embedded/Bypassable 256 character Transmit and Receive FIFOs 50-to-200 MBaud serial signaling rate Internal PLLs with no external PLL components Dual differential PECL-compatible serial inputs and outputs Compatible with fiber-optic modules and copper cables Built-In Self-Test (BIST) for link testing Link Quality Indicator Single +5.0V 10%supply 100-pin TQFP improve its serial transmission characteristics. These encoded characters are then serialized, converted to NRZI, and output from two PECL compatible differential transmission line drivers at a bit-rate of either 10 or 20 times the input reference clock in 8-bit (or 10-bit bypass) mode, or 12 or 24 times the reference clock in 10-bit (or 12-bit bypass) mode. The receive section of the CY7C9689 HOTLink accepts a serial bit-stream from one of two PECL compatible differential line receivers and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The recovered bit stream is converted from NRZI to NRZ, deserialized, framed into characters, 4B/5B or 5B/6B decoded, and checked for transmission errors. The recovered 8- or 10-bit decoded characters are then written to an internal Receive FIFO, and presented to the destination host system. The integrated 4B/5B and 5B/6B encoder/decoder may be bypassed (disabled) for systems that present externally encoded or scrambled data at the parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is converted to and from a serial NRZI stream. The embedded FIFOs may also be bypassed (disabled) to create a reference-locked serial transmission link. For those systems requiring even greater FIFO storage capability, external FIFOs may be directly coupled to the CY7C9689 through the parallel interface without the need for additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for depth expansion through external FIFOs) or as a pipeline register extender. The FIFO configurations are optimized for transport of time-independent (asynchronous) 8- or 10-bit character-oriented data across a link. A Built-In Self-Test (BIST) pattern generator and checker allows for testing of the high-speed serial data paths in both the transmit and receive sections, and across the interconnecting links. HOTLink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-topoint serial links. Some applications include interconnecting workstations, backplanes, servers, mass storage, and video transmission equipment.
Functional Description
The CY7C9689 HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable widths and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable widths. Figure 1 illustrates typical connections between two independent host systems and corresponding CY7C9689 parts. The CY7C9689 provides enhanced technology, increased functionality, a higher level of integration, higher data rates, and lower power dissipation over the AMD AM7968/7969 TAXIchip products. The transmit section of the CY7C9689 HOTLink can be configured to accept either 8- or 10-bit data characters on each clock cycle, and stores the parallel data into an internal synchronous Transmit FIFO. Data is read from the Transmit FIFO and is encoded using embedded 4B/5B or 5B/6B encoders to
Decoder 4B/5B, 5B/6B
Encoder 4B/5B, 5B/6B
Framer Deserializer
Serializer
FIFO Receive
Data Receive System Host
Serial Link
Transmit FIFO
Transmit Data System Host
Control Status FIFO Transmit Data Transmit
CY7C9689 Encoder 4B/5B, 5B/6B Serializer
CY7C9689 Decoder 4B/5B, 5B/6B Deserializer Framer Receive FIFO
Control Status Receive Data
Serial Link
Figure 1. HOTLink System Connections
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 May 4, 1999
PRELIMINARY
CY7C9689 HOTLink Logic Block Diagram
TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXRST TXHALT TXHALF TXEMPTY TXFULL TXCLK
CY7C9689
TXBISTEN Transmit FIFO 256 Byte Encoders 4B/5B, 5B/6B Serializer CURSETA OUTA OUTB CURSETB
TX CONTROL
REFCLK RANGESEL SPDSEL
DLB TX PLL A/B RX PLL INA INB
CE
Chip Enable Control Link Quality RX CONTROL CARDET LFI
RXCLK RXHALF RXEMPTY RXFULL RXRST RXEN VLTN RXCMD[1:0] RXDATA[9:8]/RXCMD[2:3] RXDATA[7:0] RXSC/D RXMODE[1:0] RESET BYTE8/10 EXTFIFO FIFOBYP ENCBYP TEST
Decoders 4B/5B, 5B/6B Receive FIFO 256 Byte
Deserializer Framer
RFEN RXBISTEN
Operating MODE
2
PRELIMINARY
Pin Configuration
RXBISTEN CURSETB CURSETA CARDET
CY7C9689
OUTB+
OUTB-
OUTA+
OUTA-
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
TEST A/B LFI VSS DLB VLTN TXBISTEN RXCLK TXHALT RXFULL VSS REFCLK VSS VDD VSS TXRST VDD TXEN RXHALF TXSC/D RXEMPTY TXDATA[0] RXCMD[1] RXMODE[1] RXMODE[0]
1 2 3 4 5 6 7 8 9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSSA
INA+
INB+
INA-
INB-
SPDSEL RANGESEL RFEN TXFULL CE TXHALF RXEN TXCLK RXRST VSS RXSC/D VDD VSS VDD RXDATA[0] TXEMPTY RXDATA[1] TXCMD[1] VSS TXCMD[0] VDD TXDATA[9]/TXCMD[2] RXDATA[2] VSS RESET
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CY7C9689
FIFOBYP
ENCBYP
VSS
VSS
VSS
RXDATA[9]/RXCMD[2]
RXDATA[8/RXCMD[3]]
VSS
RXCMD[0]
TXDATA[8]/TXCMD[3]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[6]
RXDATA[7]
RXDATA[6]
TXDATA[7]
RXDATA[5]
RXDATA[4]
RXDATA[3]
TXDATA[5]
3
BYTE8/10
VDD
EXTFIFO
PRELIMINARY
(
CY7C9689
Signal Description
Pin Descriptions
Pin 68 Name TXCLK I/O Characteristics TTL clock input Transmit FIFO Clock. Used to sample all Transmit FIFO and related interface signals. 44, 42, TXDATA[7:0] 40, 36, 34, 32, 30, 22 TTL input, sampled on Parallel Transmit DATA input. TXCLK or REFCLK When selected (CE=LOW and TXEN = asserted), information on these inputs is processed as DATA when TXSC/D is LOW and ignored otherwise. When the encoder is bypassed (ENCBYP is LOW), TXDATA[7:0] functions as the least significant eight bits of the 10- or 12-bit pre-encoded transmit character. When the Transmit FIFO is enabled (FIFOBYP is HIGH), these inputs are sampled on the rising edge of TXCLK. When the Transmit FIFO is bypassed (FIFOBYP is LOW) these inputs are captured on the rising edge of REFCLK. 54, 46 TXDATA[9:8]/ TXCMD[2:3] TTL input, sampled on Parallel Transmit DATA or COMMAND input. TXCLK or REFCLK When selected, BYTE8/10 is HIGH, and the encoder is enabled (ENCBYP is HIGH), information on these inputs are processed as TXCMD[2:3] if TXSC/D is HIGH and ignored otherwise. When selected, BYTE8/10 is LOW, and the encoder is enabled (ENCBYP is HIGH), information on these inputs are processed as TXDATA[9:8] if TXSC/D is LOW and ignored otherwise. When the encoder is bypassed (ENCBYP is LOW), TXDATA[9:8] functions as the 9th and 10th bits of the 10- or 12-bit pre-encoded transmit character. When the Transmit FIFO is enabled (FIFOBYP is HIGH), these inputs are sampled on the rising edge of TXCLK. When the Transmit FIFO is bypassed (FIFOBYP is LOW), these inputs are captured on the rising edge of REFCLK. 58, 56 TXCMD[1:0] TTL input, sampled on Parallel Transmit COMMAND input. TXCLK or REFCLK When selected and the encoder is enabled (ENCBYP is HIGH), information on these inputs is processed as a COMMAND when TXSC/D is HIGH and ignored otherwise. When BYTE8/10 is HIGH and the encoder is bypassed (ENCBYP is LOW), the TXCMD[1:0] inputs are ignored. When BYTE8/10 is LOW and when the encoder is bypassed (ENCBYP is LOW), the TXCMD[1:0] inputs function as the 11th and 12th (MSB) bits of the 12-bit pre-encoded transmit character. When the Transmit FIFO is enabled (FIFOBYP is HIGH), these inputs are sampled on the rising edge of TXCLK. When the Transmit FIFO is bypassed (FIFOBYP is LOW), these inputs are sampled on the rising edge of REFCLK. 20 TXSC/D TTL input, sampled on COMMAND or DATA input selector. TXCLK or REFCLK When selected, BYTE8/10 is HIGH, and the encoder is enabled (ENCBYP is HIGH), this input selects if the DATA or COMMAND inputs are processed. If TXSC/D is HIGH, the value on TXCMD[3:0] is captured as one of sixteen possible COMMANDs, and the data on the TXDATA[7:0] bits are ignored. If TXSC/D is LOW, the information on TXDATA[7:0] is captured as one of 256 possible 8bit DATA values, and the information on the TXCMD[3:0] bus is ignored. When BYTE8/10 is LOW and the encoder is enabled (ENCBYP is HIGH) this input selects if the DATA or COMMAND inputs are processed. If TXSC/D is HIGH, the information on TXCMD[1:0] is captured as one of four possible COMMANDs, and the information on the TXDATA[9:0] bits are ignored. If TXSC/D is LOW, the information on TXDATA[9:0] is captured as one of 1024 possible 10bit DATA values, and the information on the TXCMD[1:0] bus is ignored. When the encoder is bypassed (ENCBYP is LOW) TXSC/D is ignored Transmit Path Signals
4
PRELIMINARY
Pin Descriptions (continued)
Pin 18 Name TXEN I/O Characteristics Signal Description
CY7C9689
TTL input, sampled on Transmit Enable. TXCLK or REFCLK TXEN is sampled on the rising edge of the TXCLK or REFCLK input and enables parallel data bus write operations (when selected). The device is selected when TXEN is asserted during a clock cycle immediately following one in which CE is sampled LOW. Depending on the level on EXTFIFO, the asserted state for TXEN can be active HIGH or active LOW. If EXTFIFO is LOW, then TXEN is active LOW and data is captured on the same clock cycle where TXEN is sampled LOW. If EXTFIFO is HIGH, then TXEN is active HIGH and data is captured on the clock cycle following any clock edge when TXEN is sampled HIGH.
7
TXBISTEN
TTL input, asynchronous
Transmitter BIST Enable. When TXBISTEN is LOW, the transmitter generates a 511-character repeating sequence, that can be used to validate link integrity. This 4B/5B BIST sequence is generated regardless of the state of other configuration inputs. The transmitter returns to normal operation when TXBISTEN is HIGH. All Transmit FIFO read operations are suspended when BIST is active.
16
TXRST
TTL input, sampled on Reset Transmit FIFO. TXCLK When the Transmit FIFO is enabled (FIFOBYP is HIGH), TXEN is deasserted, CE is asserted (LOW), and TXRST is sampled LOW by TXCLK for seven cycles, the Transmit FIFO begins its internal reset process. The Transmit FIFO TXFULL flag is asserted and the host interface counter and address pointer are zeroed. This reset propagates to the serial transmit side, any remaining counters and pointers. The TXFULL flag is asserted until both sides of the Transmit FIFO have reset. While TXRST remains asserted, the Transmit FIFO remains in reset and the TXFULL output remains asserted. When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. TTL input, sampled on Transmitter Halt control input. TXCLK When TXHALT is asserted LOW, transmission of data is suspended and the HOTLink TAXI transmits SYNC characters. When TXHALT is deasserted HIGH, normal data processing proceeds. If the Transmit FIFO is enabled (FIFOBYP is HIGH), the interface is allowed to continue loading data into the Transmit FIFO while TXHALT is asserted.
9
TXHALT
72
TXFULL
Three-state TTL out- Transmit FIFO Full status flag. put, changes following When the Transmit FIFO is enabled (FIFOBYP is HIGH) and its flags are driven TXCLK or REFCLK (CE is LOW), TXFULL is asserted when four or fewer characters can be written to the HOTLink Transmit FIFO. If a Transmit FIFO reset has been initiated (TXRST was sampled asserted for a minimum of seven TXCLK cycles), TXFULL is asserted to enforce the full/unavailable status of the Transmit FIFO during reset. When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output changes after the rising edge of REFCLK. TXFULL is asserted when the transmitter is BUSY (not accepting a new data or command characters) and deasserted when new characters can be accepted. When the Transmit FIFO is bypassed and RANGESEL is HIGH or SPDSEL is LOW, TXFULL toggles at the character rate to provide a character rate reference control-indication since REFCLK is operating at twice of the data rate. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When EXTFIFO is HIGH, TXFULL is active HIGH.
5
PRELIMINARY
Pin Descriptions (continued)
Pin 70 Name TXHALF I/O Characteristics Signal Description
CY7C9689
Three-state TTL out- Transmit FIFO Half-full status flag. put, changes following When the Transmit FIFO is enabled (FIFOBYP is HIGH and CE is LOW) TXCLK TXHALF is asserted when the HOTLink Transmit FIFO is half full (128 characters is half full). If a Transmit FIFO reset has been initiated (TXRST was sampled asserted for a minimum of seven TXCLK cycles), TXHALF is asserted to enforce the full/unavailable status of the Transmit FIFO during reset. When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXHALF remains deasserted, having no logical function. TXHALF is forced to the High-Z state only during a "full-chip" reset (i.e., while RESET is LOW).
60
TXEMPTY
Three-state TTL out- Transmit FIFO Empty status flag. put, changes following When the Transmit FIFO is enabled (FIFOBYP is HIGH and CE is LOW), TXCLK or REFCLK TXEMPTY is asserted when the HOTLink Transmit FIFO has no data to forward to the encoder. If a Transmit FIFO reset has been initiated (TXRST was sampled asserted for a minimum of seven TXCLK cycles), TXEMPTY is deasserted and remains deasserted until the Transmit FIFO reset operation is complete. When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXEMPTY is asserted to indicate that the transmitter can accept data. TXEMPTY is also used as a BIST progress indicator when TXBISTEN is asserted. When TXBISTEN is asserted LOW, TXEMPTY becomes the transmit BIST-loop counter indicator (regardless of the logic state of FIFOBYP). In this mode TXEMPTY is asserted for one TXCLK or REFCLK period at the end of each transmitted BIST sequence. NOTE: During BIST operations, when the Transmit FIFO is enabled (FIFOBYP is HIGH), it is necessary to keep TXCLK operating, even though no data is loaded into the Transmit FIFO and TXEN is never asserted, to allow the TXEMPTY flag to respond to the BIST state changes. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, TXEMPTY is active LOW. When EXTFIFO is HIGH, TXEMPTY is active HIGH. If CE is sampled asserted (LOW), TXEMPTY is driven to an active state. If CE is sampled deasserted (HIGH), TXEMPTY is placed into a High-Z state.
Receive Path Signals 8 RXCLK Bidirectional TTL clock Receive clock. When the Receive FIFO is enabled (FIFOBYP is HIGH), this clock is the Receive interface input clock and is used to control Receive FIFO read and reset, operations. When the Receive FIFO is bypassed (FIFOBYP is LOW), this clock becomes the recovered Receive PLL character clock output which runs continuously at the character rate. 41, 43, RXDATA[7:0] 45, 47, 48, 53, 59,61 Three-state TTL out- Parallel Receive DATA outputs. put, changes following When the decoder is enabled (ENCBYP is HIGH), the low-order eight bits of RXCLK the decoded DATA character are presented on the RXDATA[7:0] outputs. COMMAND characters, when they are received, do not disturb these outputs. When the decoder is bypassed, the low order eight bits of the non-decoded character are presented on the RXDATA[7:0] outputs. When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change on the rising edge of the RXCLK output. When the Receive FIFO is enabled (FIFOBYP is HIGH), these outputs change on the rising edge of RXCLK input. RXEN is the three-state control for RXDATA[7:0].
6
PRELIMINARY
Pin Descriptions (continued)
Pin Name I/O Characteristics Signal Description 31, 33 RXDATA[9:8]/ RXCMD[2:3]
CY7C9689
Three-state TTL out- Parallel Receive DATA or COMMAND output. put, changes following When BYTE8/10 is HIGH and the decoder is enabled (ENCBYP is HIGH) these RXCLK outputs reflects the value for the most recently received RXCMD[2:3]. When BYTE8/10 is LOW and the decoder is enabled (ENCBYP is HIGH) these outputs reflects the value for the most recently received RXDATA[9:8]. When the decoder is bypassed (ENCBYP is LOW), RXDATA[9:8] functions as the 9th and 10th bits of the 10- or 12-bit non-decoded receive character. When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change on the rising edge of the RXCLK output. When the Receive FIFO is enabled (FIFOBYP is HIGH), these outputs change on the rising edge of the RXCLK input. RXEN is a three-state control for RXDATA[9:8]/RXCMD[2:3].
23, 29 RXCMD[1:0]
Three-state TTL out- Parallel Receive COMMAND outputs. put, changes following When the decoder is enabled (ENCBYP is HIGH) these outputs reflect the value RXCLK for the most recently received RXCMD[1:0]. When BYTE8/10 is HIGH and the decoder is bypassed (ENCBYP is LOW), these outputs have no meaning and are driven LOW. When BYTE8/10 is LOW and the decoder is bypassed (ENCBYP is LOW), RXCMD[1:0] functions as the 11th and 12th (MSB) bits of the 12-bit nondecoded receive character. When the Receive FIFO is disabled (FIFOBYP is LOW), this output changes on the rising edge of the RXCLK output. When the Receive FIFO is enabled (FIFOBYP is HIGH), these outputs change on the rising edge of the RXCLK input. RXEN is a three-state control for RXCMD[1:0].
69
RXEN
TTL input, sampled on RXCLK
Receive Enable input. RXEN is a three-state control for the parallel data bus read operations. RXEN is sampled on the rising edge of the RXCLK input (or output) and enables parallel data bus read operations (when selected). The device is selected when RXEN is asserted during an RXCLK cycle immediately following one in which CE is sampled LOW. The parallel data pins are driven to active levels after the rising edge of RXCLK. When RXEN is de-asserted (ending the selection) the parallel data pins are High-Z after the rising edge of RXCLK. Depending on the level on EXTFIFO, this signal can be active HIGH or active LOW. If EXTFIFO is LOW, then RXEN is active LOW. If EXTFIFO is HIGH, then RXEN is active HIGH. Data is delivered on the clock cycle following any clock edge when RXEN is active.
65
RXSC/D
Three-state TTL out- COMMAND or DATA output indicator. put, changes following When BYTE8/10 is HIGH and the decoder is enabled (ENCBYP is HIGH), this RXCLK output indicates which group of outputs have been updated. If RXSC/D is HIGH, RXCMD[3:0] contains a new COMMAND. The DATA on the RXDATA[7:0] pins remain unchanged. If RXSC/D is LOW, RXDATA[7:0] contains a new DATA character. The COMMAND output on RXCMD[3:0] remain unchanged. When BYTE8/10 is LOW and the decoder is enabled (ENCBYP is HIGH), this output indicates which group of outputs have been updated. If RXSC/D is HIGH, RXCMD[1:0] contains a new COMMAND and the DATA on the RXDATA[9:0] remain unchanged. If RXSC/D is LOW, RXDATA[9:0] contains a new DATA character and the COMMAND output on RXCMD[1:0] remain unchanged. When the decoder is bypassed (ENCBYP is LOW) RXSC/D is not used and may be left unconnected. RXEN is a three-state control for RXSC/D.
7
PRELIMINARY
Pin Descriptions (continued)
Pin 6 Name VLTN I/O Characteristics Signal Description
CY7C9689
Three-state TTL out- Code rule violation detected. put, changes following VLTN is asserted in response to detection of a 4B/5B or 5B/6B character that RXCLK does not meet the coding rules of these characters. When VLTN is asserted, the values on the output DATA and COMMAND buses remain unchanged. VLTN remains asserted for one RXCLK period. VLTN is used to report character mismatches when RXBISTEN is driven LOW. VLTN is driven LOW when the decoder is bypassed (ENCBYP is LOW). RXEN is a three-state control for VLTN.
67
RXRST
TTL input, sampled on Receive FIFO Reset. Active LOW. RXCLK When the Receive FIFO is enabled (FIFOBYP is HIGH), RXEN is deasserted, CE is asserted (LOW), and RXRST is sampled while asserted (LOW) by RXCLK for seven cycles, the Receive FIFO begins its internal reset process. Once the reset operation is started, the RXEMPTY flag is asserted and the interface counters and address pointer are zeroed. The reset operation proceeds to clear out the internal write pointers and counters. The RXEMPTY output remains asserted through the reset operation and remains asserted until new data is written to the Receive FIFO. While RXRST remains asserted, the Receive FIFO remains in reset and cannot accept received characters. When the Receive FIFO is bypassed (FIFOBYP is LOW), RXRST is ignored.
24, 25 RXMODE[1:0] Static control input TTL levels Normally wired HIGH or LOW
Receiver Discard Policy mode select. * 00b--allows all characters to be written into the Receive FIFO or output to the Receive data bus * 01b--discards all JK or LM sync characters except the "last" one of a string of sync characters. Single sync characters in a data stream are included in the data written into the Receive FIFO. * 1Xb--discards all JK or LM sync characters. The data stream written into the Receive FIFO does not include sync characters. Receiver BIST enable. Active LOW. When LOW, the receiver is configured to perform a character-for-character match of the incoming data stream with a 511-character BIST sequence. The result of character mismatches are indicated on the VLTN pin. Completion of each 511-character BIST loop is accompanied by an assertion pulse on the RXFULL flag. , The state of ENCBYP, FIFOBYP and BYTE8/10 have no effect on BIST operation.
77
RXBISTEN
TTL input, asynchronous
73
RFEN
TTL input, asynchronous
Reframe Enable. Used to control when the framer is allowed to adjust the character boundaries based on detection of one or more framing characters in the data stream. When framing is enabled (RFEN is HIGH) the receive framer realigns the serial stream to the incoming 10-bit JK sync character (if BYTE8/10 is HIGH) or the 12-bit LM sync character (if BYTE8/10 is LOW). Framing is disabled when RFEN is LOW. The deassertion of RFEN freezes the character boundary relationship between the serial stream and character clock. RFEN is an asynchronous input, sampled by the internal Receive PLL character clock.
8
PRELIMINARY
Pin Descriptions (continued)
Pin 10 Name RXFULL I/O Characteristics Signal Description
CY7C9689
Three-state TTL out- Receive FIFO Full flag. put, changes following When the Receive FIFO is enabled (FIFOBYP is HIGH) and its flags are driven RXCLK (CE is LOW), RXFULL is asserted when space is available for four or fewer characters to be written to the HOTLink Receive FIFO. If the RXCLK input is not continuous or the FIFO is accessed at a rate slower than data is being received, RXFULL may also indicate that some data has been lost because of FIFO overflow. When the Receive FIFO is bypassed (FIFOBYP is LOW), RXFULL is deasserted to indicate that valid data may be present. RXFULL is also used as a BIST progress indicator, and pulses once every pass through the 511 character BIST loop. When RXBISTEN is asserted (LOW), RXFULL becomes the receive BIST loop progress indicator (regardless of the logic state of FIFOBYP). While RXBISTEN is asserted, RXFULL is asserted until the receiver detects the start of the BIST pattern. Then RXFULL is deasserted for the duration of the BIST pattern, pulsing asserted for one RXCLK period on the last symbol of each BIST loop. If 14 of 28 consecutive symbols are received in error, RXFULL returns to the asserted state until the start of a BIST pattern is again detected. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, RXFULL is active LOW. When EXTFIFO is HIGH, RXFULL is active HIGH.
19
RXHALF
Three-state TTL out- Receive FIFO Half-full flag. put, changes following When the Receive FIFO is enabled (FIFOBYP is HIGH and CE is LOW) RXCLK RXHALF is asserted when the HOTLink Receive FIFO is half full (128 characters is half full). If a Receive FIFO reset has been initiated (RXRST was sampled asserted for a minimum of seven RXCLK cycles), RXHALF is deasserted to enforce the empty/unavailable status of the Receive FIFO during reset. If FIFOBYP is LOW, RXHALF remains deasserted having no logical function. RXHALF is forced to the High-Z state only during a "full-chip" reset (i.e., while RESET is LOW).
21
RXEMPTY
Three-state TTL out- Receive FIFO Empty flag. put, changes following When the Receive FIFO is enabled (FIFOBYP is HIGH) and its flags are driven RXCLK (CE is LOW), RXEMPTY is asserted when the HOTLink Receive FIFO has no data to forward to the parallel interface. If a Receive FIFO reset has been initiated (RXRST was sampled asserted for a minimum of seven RXCLK cycles), RXEMPTY is asserted to enforce the empty/unavailable status of the Receive FIFO during reset. Any read operation occurring when RXEMPTY is asserted results in no change in the FIFO status, and the data from the last valid read remains on the RXDATA bus. When the Receive FIFO is bypassed but the decoder is enabled, RXEMPTY is used as a valid data indicator. When deasserted it indicates that valid data is present at the RXDATA or RXCMD outputs as indicated by RXSC/D. When asserted it indicates that a SYNC character (JK or LM) is present on the RXCMD output pins. When the Receive FIFO is bypassed (FIFOBYP is LOW), RXEMPTY is deasserted whenever data is ready. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, RXEMPTY is active LOW. When EXTFIFO is HIGH, RXEMPTY is active HIGH.
9
PRELIMINARY
Pin Descriptions (continued)
Pin 71 CE Name I/O Characteristics Signal Description Control Signals
CY7C9689
TTL input sampled on Chip Enable input. Active LOW. TXCLK, RXCLK, or When CE is asserted and sampled LOW by RXCLK, the Receive FIFO status REFCLK flags are driven to their active states. When this input is deasserted and sampled by RXCLK, the Receive FIFO status flags are placed in a High-Z state. When CE has been sampled LOW and RXEN changes from deasserted to asserted and is sampled by RXCLK, the RXSC/D, RXDATA[7:0], RXDATA[9:8]/ RXCMD[2:3] and VLTN output drivers are enabled and go to their driven levels. These pins remain driven until RXEN is sampled deasserted. When the Transmit FIFO is enabled (FIFOBYP is HIGH), and CE is asserted and sampled by TXCLK, the Transmit FIFO status flags are driven to their active states. When this input is deasserted and sampled by TXCLK, the Transmit FIFO status flags are placed in a High-Z state. When the Transmit FIFO is bypassed (FIFOBYP is LOW), and CE is asserted and sampled by REFCLK, the Transmit FIFO status flags are driven to their active states. When this input is deasserted and sampled by REFCLK, the Transmit FIFO status flags are placed in a High-Z state. When the Transmit FIFO is enabled (FIFOBYP is HIGH), CE has been sampled LOW, and TXEN changes from deasserted to asserted and is sampled by TXCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and TXCMD[1:0] inputs are sampled and passed to the Transmit FIFO. These inputs are sampled on all consecutive TXCLK cycles until TXEN is sampled deasserted. When the Transmit FIFO is bypassed (FIFOBYP is LOW), CE has been sampled LOW, and TXEN changes from deasserted to asserted and is sampled by REFCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and TXCMD[1:0] inputs are sampled and passed to the encoder or serializer as directed by other control inputs. These inputs are sampled on all consecutive REFCLK cycles until TXEN is sampled deasserted.
12
REFCLK
TTL clock input
PLL Frequency Reference clock. This clock input is used as the timing reference for the transmit and receive PLLs. When the Transmit FIFO is bypassed (FIFOBYP is HIGH), REFCLK is also used as the clock for the parallel transmit interface.
75
SPDSEL
Static control input TTL levels Normally wired HIGH or LOW Static control input TTL levels Normally wired HIGH or LOW
Speed select. Used to select from one of two operating serial rates for the CY7B9689. When SPDSEL is HIGH, the signaling rate is between 100 and 200 MBaud. When LOW, the signaling rate is between 50 and 100 MBaud. Used in combination with RANGESEL and BYTE8/10 to configure the VCO multipliers and dividers. Range select. Selects the proper prescaler for the REFCLK input. If RANGESEL is LOW, the REFCLK input is passed directly to the Transmit PLL clock multiplier. If RANGESEL is HIGH, REFLCK is divided by two before being sent to the Transmit PLL multiplier. When the Transmit FIFO is bypassed (FIFOBYP is LOW), with RANGESEL HIGH or SPDSEL LOW, TXFULL toggles at half the REFCLK rate to provide a character rate indication, and to show when data can be accepted.
74
RANGESEL
51
RESET
Asynchronous TTL input
Master Reset for internal logic. Pulsed LOW for one or more REFCLK cycles.
10
PRELIMINARY
Pin Descriptions (continued)
Pin 28 Name FIFOBYP I/O Characteristics Static control input TTL levels Normally wired HIGH or LOW FIFO Bypass enable. Signal Description
CY7C9689
When asserted, the Transmit and Receive FIFOs are bypassed. In this mode TXCLK is not used. Instead all transmit data must be synchronous to REFCLK. Transmit FIFO status flags are synchronized to REFCLK. All received data is synchronous to RXCLK output. Receive FIFO status flags are synchronized to RXCLK (the recovered Receive PLL character clock). When not asserted, the Transmit and Receive FIFOs are enabled. In this mode all Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO reads are synchronous to the RXCLK input.
50
BYTE8/10
Static control input TTL levels Normally wired HIGH or LOW
8/10-bit Parallel Data Size select. When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is enabled (ENCBYP is HIGH), 8-bit DATA characters and 4-bit COMMAND characters are captured at the TXDATA[7:0] or TXCMD[3:0] inputs (selected by the TXSC/D input) and passed to the Transmit FIFO (if enabled) and encoder. Received characters are decoded, passed through the Receive FIFO (if enabled) and presented at either the RXDATA[7:0] or RXCMD[3:0] outputs and indicated by the RXSC/D output. When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is bypassed (ENCBYP is LOW), the internal data paths are set for 10-bit characters. Each received character is presented to the Receive FIFO (if enabled) and is passed to the RXDATA[9:0] outputs. When set for 10-bit data (BYTE8/10 is LOW) and the encoder is enabled (ENCBYP is HIGH), 10-bit DATA characters and 2-bit COMMAND characters are captured at the TXDATA[9:0] or TXCMD[1:0] inputs (selected by the TXSC/D input) and passed to the Transmit FIFO (if enabled) and encoder. Received characters are decoded, passed through the Receive FIFO (if enabled) and presented at either the RXDATA[9:0] or RXCMD[1:0] outputs and indicated by the RXSC/D output. When set for 10-bit data (BYTE8/10 is LOW) and the encoder is bypassed (ENCBYP is LOW), the internal clock data paths are set for 12-bit characters. Each received character is presented to the Receive FIFO (if enabled) and is passed to the RXDATA[9:0] and the RXCMD[1:0] outputs.
49
EXTFIFO
Static control input TTL levels Normally wired HIGH or LOW
External FIFO mode. EXTFIFO modifies the active state of the RXEN and TXEN inputs and the timing of the Transmitter and Receiver data buses. When configured for external FIFOs (EXTFIFO is HIGH), TXEN is assumed to be driven by the empty flag of an attached CY7C42X5 FIFO, and RXEN is assumed to be driven by the almost full flag of an attached CY7C42X5 FIFO. In this mode the active data transition is in the clock following the clock edge that "enables" the data bus. When not configured for external FIFOs (EXTFIFO is LOW), TXEN is assumed to be driven as a pipeline register and RXEN is assumed to be driven by a controller for a pipeline register. In this mode the active data transition is within the same clock as the clock edge that "enables" the data bus. EXTFIFO also modifies the output state of the Receive and Transmit FIFO flags. When configured for external FIFOs (EXTFIFO is HIGH), the Full and EMPTY FIFO flags are active HIGH (the Half full flag is always active LOW). When not configured for external FIFOs (EXTFIFO is LOW), all of the FIFO flags are active LOW.
27
ENCBYP
Static control input TTL levels Normally wired HIGH or LOW
Enable Encoder Bypass mode. When asserted, both the encoder and decoder are bypassed. Data is transmitted without 4B/5B or 5B/6B encoding (but with NRZI encoding), LSB first. Received data are presented as parallel characters to the parallel interface without decoding. When deasserted, data is passed through both the encoder in the Transmit path and the decoder in the Receive path.
11
PRELIMINARY
Pin Descriptions (continued)
Pin Name I/O Characteristics PECL compatible differential output Signal Description Differential Serial Data outputs. Analog I/O and Control 89, 90, OUTA 81, 82 OUTB
CY7C9689
These PECL-compatible differential outputs are capable of driving terminated transmission lines or commercial fiberoptic transmitter modules. To minimize the power dissipation of unused outputs, the outputs should be left unconnected and the associated CURSETA or CURSETB should be connected to V DD. Differential Serial Data inputs. These inputs accept the serial data stream for deserialization and decoding. Only one serial stream at a time may be fed to the receive PLL to extract the data content. This stream is selected using the A/B input. Current-set resistor input for OUTA. A precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the OUTA differential driver.
85, 86, INA 93, 94 INB
PECL compatible differential input
97
CURSETA
Analog
78
CURSETB
Analog
Current-set resistor input for OUTB. A precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the OUTB differential driver.
100
CARDET
PECL input, asynchronous
Carrier detect input. Used to allow an external device to signify a valid signal is being presented to the high speed PECL input buffers, as is typical on an Optical Module. When CARDET is deasserted LOW, the LFI indicator asserts LOW signifying a Link Fault. This input can be tied HIGH for copper media applications. Input A or Input B selector. When HIGH, input INA is selected, when LOW, INB is selected.
2 3
A/B LFI
Asynchronous TTL input
Three-state TTL out- Link Fault Indication output. Active LOW. put, changes following LFI changes synchronous with RXCLK. This output is driven LOW when the RXCLK serial link currently selected by A/B is not suitable for data recovery. This could be because: 1. Serial Data Amplitude is below acceptable levels 2. Input transition density is not sufficient for PLL clock recovery 3. Input Data stream is outside an acceptable frequency range of operation 4. CARDET is LOW
5
DLB
Asynchronous TTL input
Diagnostic Loop Back selector. When DLB is LOW, LOOP Mode is OFF. Output of the transmitter shifter is routed to both OUTA and OUTB and the serial input selected by A/B is routed to the receive PLL for data recovery. When DLB is HIGH, Diagnostic Loopback is Enabled. Output of the transmitter serial data is routed to the receive PLL for data recovery. Primarily used for System Diagnostic test. The serial inputs are ignored and OUTA and OUTB are both active.
1
TEST
Asynchronous TTL input normally wired HIGH
Test Mode select. Used to force the part into a diagnostic test mode used for factory ATE test. This input must be tied HIGH during normal operation. Power for PECL compatible I/O signals and internal circuits.
Power 80, 87, VDDA 88, 95, 96 76, 79, VSSA 83, 84, 91, 92, 99
Ground for PECL compatible I/O signals and internal circuits.
12
PRELIMINARY
Pin Descriptions (continued)
Pin 14, 17, VDD 35, 55, 62, 64 4,11, VSS 13, 15, 26, 37, 38, 39, 52, 57, 63, 66 Table 1. Transmit Input Bus Signal Map Transmit Encoder Mode[1] TXDATA Bus Input Bit TXSC/D TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXDATA[8]/TXCMD[3] TXDATA[9]/TXCMD[2] TXCMD[1] TXCMD[0] Encoded 8-bit Character Stream[2] TXSC/D TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXCMD[3] TXCMD[2] TXCMD[1] TXCMD[0] TXD[0]
[4]
CY7C9689
Signal Description
Name
I/O Characteristics
Power for TTL I/O signals and internal circuits.
Ground for TTL I/O signals and internal circuits.
Pre-encoded 10-bit Character Stream
Encoded 10-bit Character Stream[3] TXSC/D TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXDATA[8] TXDATA[9][3] TXCMD[1] TXCMD[0]
Pre-encoded 12-bit Character Stream TXD[0][5] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] TXD[10][5] TXD[11]
TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9]
Notes: 1. All open cells are ignored. 2. When ENCBYP is HIGH and BYTE8/10 is HIGH, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[7,6,5,4] and TXDATA[3,2,1,0] or TXCMD[3,2,1,0] as selected by TXSC/D. 3. When ENCBYP is HIGH and BYTE8/10 is LOW, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[8,7,6,5,4] and TXDATA[9,3,2,1,0] or TXCMD[1,0] as selected by TXSC/D. 4. When ENCBYP is LOW and BYTE8/10 is HIGH, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9]. 5. When ENCBYP is LOW and BYTE8/10 is LOW, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9,11,10].
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PRELIMINARY
. Table 2. Receiver Output Bus Signal Map Receiver Decoder Mode[1] RXDATA Bus Output Bit RXSC/D RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXDATA[8]/RXCMD[3] RXDATA[9]/RXCMD[2] RXCMD[1] RXCMD[0] VLTN Encoded 8-bit Character Stream[7] RXSC/D RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXCMD[3] RXCMD[2] RXCMD[1] RXCMD[0] VLTN RXD[0]
[6, 9]
CY7C9689
Pre-encoded 10-bit Character Stream
Encoded 10-bit Character Stream[8] RXSC/D RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXDATA[8] RXDATA[9]
[8]
Pre-encoded 12-bit Character Stream RXD[0][6, 10] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[9] RXD[10][10] RXD[11]
RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[9]
RXCMD[1] RXCMD[0] VLTN
Notes: 6. First bit shifted into the receiver. 7. When BYTE8/10 is HIGH, received bit order is decoded form the serial stream and presented (MSB to LSB) at RXDATA[7,6,5,4] and RXDATA[3,2,1,0] or RXCMD[3,2,1,0] as indicated by RXSC/D 8. When BYTE8/10 is LOW, received bit order is decoded form the serial stream and presented (MSB to LSB) at RXDATA[8,7,6,5,4] and RXDATA[9,3,2,1,0] or RXCMD[1,0] as indicated by RXSC/D 9. When ENCBYP is LOW and BYTE8/10 is HIGH, the received bit order is (LSB to MSB) RXD[0,1,2,3,4,5,6,7,8,9]. 10. When ENCBYP is LOW and BYTE8/10 is LOW, the received bit order is (LSB to MSB) RXD[0,1,2,3,4,5,6,7,8,9,11,10].
CY7C9689 HOTLink Operation
Overview The CY7C9689 is designed to move parallel data across both short and long distances with minimal overhead or host system intervention. This is accomplished by converting the parallel characters into a serial bit-stream, transmitting these serial bits at high speed, and converting the received serial bits back into the original parallel data format. The CY7C9689 offers a large feature set, allowing it to be used in a wide range of host systems. Some of the of configuration options are * AMD TAXIchip 4B/5B & 5B/6B compatible encoder/decoder * AMD TAXIchip compatible serial link * AMD TAXIchip parallel COMMAND and DATA I/O bus architecture * 8-bit or 10-bit character size * User-definable data packet or frame structure * Two-octave data rate range * Asynchronous (FIFOed) or synchronous data interface * Embedded or bypassable FIFO data storage * Encoded or non-encoded * Multi-PHY capability This flexibility allows the CY7C9689 to meet the data transport needs of almost any system.
Transmit Data Path Transmit Data Interface/Transmit Data FIFO The transmit data interface to the host system is configurable as either an asynchronous buffered (FIFOed) parallel interface or as a synchronous pipeline register. The bus itself can be configured for operation with either 8-bit or 10-bit character widths. When configured for asynchronous operation (where the hostbus interface clock operates asynchronous to the serial character and bit stream clocks), the host interface becomes that of a synchronous FIFO clocked by TXCLK. In this configuration an internal 256 character Transmit FIFO is enabled that allows the host interface to be written at any rate from DC to 50 MHz. When configured for synchronous operation, the transmit interface is clocked by REFCLK and operates synchronous to the internal character and bit-stream clocks. The input register can be written at either 1/10th or 1/12th the serial bit rate. This interface can be clocked at up to 40 MHz when configured for 8-bit data width, and up to 33 MHz when configured for 10-bit data bus width. Actual clock rate depends on data rate as well as RANGESEL and SPDSEL logic levels. Both asynchronous and synchronous interface operations support user control over the logical sense of the FIFO status flags. Full and empty flags on both the transmitter and receiver can be active HIGH or active LOW. This facilitates interfacing
14
PRELIMINARY
with existing control logic or external FIFOs with minimal or no external glue logic. Encoder Data from the host interface or Transmit FIFO is next passed to an Encoder block. The CY7C9689 contains both 4B/5B and 5B/6B encoders that are used to improve the serial transport characteristics of the data. For those systems that contain their own encoder or scrambler, this Encoder may be bypassed. Serializer/Line Driver The data from the Encoder is passed to a Serializer. This Serializer operates at 10 or 12 times the character rate. With the internal FIFOs enabled, REFCLK can run at 1x, 2x, or 4x the character rate. With the FIFOs bypassed, REFCLK can operate at 1x or 2x the character rate. The serialized data is output in NRZI format from two PECL-compatible differential line drivers configured to drive transmission lines or optical modules. Receive Data Interface Line Receiver/Deserializer/Framer Serial data is received at one of two PECL-compatible differential line receivers. The data is passed to both a Clock and Data Recovery Phase Locked Loop (PLL) and to a Deserializer that converts NRZI serial data into NRZ parallel characters. The Framer adjusts the boundaries of these characters to match those of the original transmitted characters. Decoder The parallel characters are passed through a pair of 5B/4B or 6B/5B Decoders and returned to their original form. For systems that make use of external decoding or descrambling, the decoder may be bypassed. Receive Data Interface/Receive Data FIFO Data from the decoder is passed either to a synchronous Receive FIFO or is passed directly to the output register. The output register can be configured for either 8-bit character or 10-bit character operation.
CY7C9689
When configured for an asynchronous buffered (FIFOed) interface, the data is passed through a 256-character Receive FIFO that allows data to be read at any rate from DC to 50 MHz. When configured for synchronous operation (Receive FIFO is bypassed) data is clocked out of the Receive Output register at up to 20 MHz when configured for 8-bit characters, or 16.67 MHz when configured for 10-bit characters. The receive interface is also configurable for FIFO flags with either HIGH or LOW status indication Oscillator Speed Selection The CY7B9689 is designed to operate over a two-octave range of serial signaling rates, covering the 50- to 200-MBaud range. To cover this wide range, the PLLs are configured into various sub-regions using the SPDSEL and RANGESEL inputs, and to a limited extent the BYTE8/10 input. These inputs are used to configure the various prescalers and clock dividers used with the transmit and receive PLLs.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with (Power Applied) -55C to +125C Supply Voltage to Ground Potential................-0.5V to +6.5V DC Voltage Applied to Outputs................ -0.5V to VDD+0.5V Output Current into TTL Outputs (LOW) ..................... 30 mA DC Input Voltage ..................................... -0.5V to VDD+0.5V Static Discharge Voltage................................................> 2001V (per MIL-STD-883, Method 3015) Latch-Up Current...........................................................> 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 5.0V 10% 5.0V 10%
15
PRELIMINARY
CY7C9689 DC Electrical Characteristics Over the Operating Range
Parameter TTL Outputs VOHT VOLT IOST TTL Inputs VIHT VILT IIHT IILT IILPUT Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input LOW Current with Internal Pull-Up Output HIGH Voltage (VDD referenced) Output LOW Voltage (VDD referenced) Output Differential Voltage |(OUT+) - (OUT-)| Input HIGH Voltage (VDD referenced) Input LOW Voltage (VDD referenced) Input Differential Voltage |(IN+) - (IN-)| Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Power Supply Current VIN = VIHH Max. VIN = VILL Min. Freq. = Max. Commercial -200 Typ. TBD 2.5 VIN = VDD VIN = 0.0V VIN = 0.0V 2.0 Output HIGH Voltage Output LOW Voltage Output Short Circuit Current IOH = -2 mA, VDD = Min IOL = 8 mA, VDD = Min VOUT = 0V
[11]
CY7C9689
Description
Test Conditions
Min. 2.4
Max.
Unit V
0.4 -30 -80
V mA V
0.8 +40 + 40 -500
V A A A
Transmitter PECL-Compatible Output Pins: OUTA+, OUTA-, OUTB+, OUTB- VOHE VOLE VODIF Load = 50 to VDD - 1.33V RCURSET=TBD Load = 50 to VDD - 1.33V RCURSET=TBD Load = 50 ohms to VDD - 1.33V RCURSET=TBDmin - TBDmax VDD-1.03 VDD-2.0 600 VDD-0.83 VDD-1.62 1100 V V mV
Receiver Single-ended PECL-Compatible Input Pin: CARDET VIHE VILE VDD-1.165 2.5 VDD VDD-1.475 V V
Receiver Differential Line Receiver Input Pins: INA+, INA-, INB+, INB- VDIFF VIHH VILL IIHH IILL[12] IDD[13] 200 2500 VDD 750 Max. 250 mA mV V V A A
Miscellaneous
Capacitance[14]
Parameter CINTTL CINPECL Description TTL Input Capacitance PECL input Capacitance Test Conditions TA = 25C, f0 = 1 MHz, V DD = 5.0V TA = 25C, f0 = 1 MHz, V DD = 5.0V Max. 7 4 Unit pF pF
Notes: 11. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 12. To guarantee positive currents for all PECL voltages, an external pull-down resistor must be present. 13. Maximum I CC is measured with VDD = MAX, RFEN = LOW, and outputs unloaded. Typical IDD is measured with VDD = 5.0V, TA = 25C, RFEN = LOW, and outputs unloaded. 14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
16
PRELIMINARY
AC Test Loads and Waveforms
5.0V OUTPUT R1=500 R2=333 CL 10 pF (Includes fixture and probe capacitance) CL R2
[15] [15]
CY7C9689
R1 CL RL
VDD - 1.3
RL =50 CL < 5 pF (Includes fixture and probe capacitance)
(a) TTL AC Test Load
3.0V Vth =1.5V 0.0V < 1 ns 2.0V 0.8V 3.0V 2.0V 0.8V
(b) PECL AC Test Load
VIHE
VIHE 80% 80% 20% VILE 250 ps 20%
Vth =1.5V VILE < 1 ns
250 ps
(c) TTL Input Test Waveform
(d) PECL Input Test Waveform
CY7C9689 Transmitter TTL Switching Characteristics, FIFO Enabled Over the Operating Range
Parameter fTS tTXCLK tTXCPWH tTXCPWL tTXCLKR tTXCLKF tTXA tTXDS tTXDH tTXENS tTXENH tTXRSS tTXRSH tTXCES tTXCEH tTXZA tTXOE tTXAZ TXCLK Period TXCLK HIGH Time TXCLK LOW Time TXCLK Rise Time TXCLK Fall Time Flag Access Time From TXCLK to output Transmit Data Set-Up Time to TXCLK Transmit Data Hold Time from TXCLK Transmit Enable Set-Up Time to TXCLK Transmit Enable Hold Time from TXCLK Transmit FIFO Reset (TXRST) Set-Up Time to TXCLK Transmit FIFO Reset (TXRST Hold Time from TXCLK Transmit Chip Enable (CE) Set-Up Time to TXCLK Transmit Chip Enable (CE) Hold Time from TXCLK Sample of CE LOW by TXCLK, Output High-Z to active HIGH or LOW Sample of CE LOW by TXCLK to Output Valid Sample of CE HIGH by TXCLK to Output in High-Z Description TXCLK Clock Cycle Frequency With Transmit FIFO Enabled 20 6.5 6.5 0.7 0.7 4 4 1 4 1 4 1 4 1 0 2 2 20 20 5 5 15 Min. Max 50 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 15. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
17
PRELIMINARY
CY7C9689
CY7C9689 Receiver TTL Switching Characteristics, FIFO Enabled Over the Operating Range
Parameter fRIS tRXCLKIP tRXCPWH tRXCPWL tRXCLKIR tRXCLKIF tRXENS tRXENH tRXRSS tRXRSH tRXCES tRXCEH tRXA tRXZA Description RXCLK Clock Cycle Frequency With Receive FIFO Enabled RXCLK Input Period RXCLK Input HIGH Time RXCLK Input LOW Time RXCLK Input Rise Time RXCLK Input Fall Time Receive Enable Set-Up Time to RXCLK Receive Enable Hold Time from RXCLK Receive FIFO Reset (RXRXT) Set-Up Time to RXCLK Receive FIFO Reset (RXRXT) Hold Time from RXCLK Receive Chip Enable (CE) Set-Up Time to RXCLK Receive Chip Enable (CE) Hold Time from RXCLK Flag and Data Access Time From RXCLK to Output Sample of CE LOW by RXCLK, Output High-Z to Active HIGH or LOW, or Sample of RXEN Asserted by RXCLK, Output High-Z to Active HIGH or LOW Sample of CE LOW by RXCLK to Output Valid,[16] or Sample of RXEN Asserted by RXCLK to RXDATA Outputs Valid Sample of CE HIGH by RXCLK to Output in High-Z,[16] or Sample of RXEN Asserted by RXCLK to RXDATA Outputs in High-Z
[16]
Min.
Max 50
Unit MHz ns ns ns
20 6.5 6.5 0.7 0.7 4 1 4 1 4 1 4 0 15 5 5
ns ns ns ns ns ns ns ns ns ns
tRXOE tRXZA
2 2
20 20
ns ns
Note: 16. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
CY7C9689 Transmitter TTL Switching Characteristics, FIFO Bypassed Over the Operating Range
Parameter tTRA tREFDS tREFDH tREFENS tREFENH tREFCES tREFCEH tREFZA tREFOE tREFAZ Description Flag Access Time From REFCLK to Output Write Data Set-Up Time to REFCLK Write Data Hold Time from REFCLK Transmit Enable Set-Up Time to REFCLK Transmit Enable Hold Time from REFCLK Transmit Chip Enable (CE) Set-Up Time to REFCLK Transmit Chip Enable (CE) Hold Time from REFCLK Sample of CE LOW by REFCLK, Output High-Z to Active HIGH or LOW Sample of CE LOW by REFCLK to Flag Output Valid Sample of CE HIGH by REFCLK to Flag Output High-Z Min. 4 4 1 4 1 4 1 0 2 2 20 20 Max 15 Unit ns ns ns ns ns ns ns ns ns ns
18
PRELIMINARY
CY7C9689
CY7C9689 Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range
Parameter fROS[17] Description RXCLK Clock Output Frequency--100 to 200 MBaud 8-bit Operation (SPDSEL is HIGH and BYTE8/10 is HIGH) RXCLK Clock Output Frequency--50 to 100 MBaud 8-bit Operation (SPDSEL is LOW and BYTE8/10 is HIGH) RXCLK Clock Output Frequency--100 to 200 MBaud 10-bit Operation (SPDSEL is HIGH and BYTE8/10 is LOW) RXCLK Clock Output Frequency--50 to 100 MBaud 10-bit Operation (SPDSEL is LOW and BYTE8/10 is LOW) tRXCLKOP tRXCLKOD tRXCLKOR tRXCLKOF tRXENS tRXENH tRXZA tRXOE tRXAZ RXCLK Output Period RXCLK Output Duty Cycle RXCLK Output Rise Time RXCLK Output Fall Time Receive Enable Set-Up Time to RXCLK Receive Enable Hold Time from RXCLK Sample of CE LOW by RXCLK, Outputs High-Z to Active Sample of RXEN Asserted by RXCLK to RXDATA Outputs High-Z to Active Sample of CE LOW by RXCLK to Flag Output Valid Sample of RXEN Asserted by RXCLK to RXDATA Output Low-Z Sample of CE HIGH by RXCLK to Flag Output High-Z Sample of RXEN Deasserted by RXCLK to RXDATA Output High-Z Min. 10 5 8.33 4.16 25 40 0.5 0.5 4 1 0 2 2 20 20 Max 20 10 16.67 8.33 240 60 2 2 Unit MHz MHz MHz MHz ns % ns ns ns ns ns ns ns
Notes: 17. The period of tROS will match the period of the transmitter PLL reference (REFCLK) when receiving serial data. When data is interrupted, RXCLK may drift to REFCLK +0.2%.
19
PRELIMINARY
CY7C9689 REFCLK Input Switching Characteristics Over the Operating Range
Conditions Parameter fREF Description REFCLK Clock Frequency--50 to 100 MBaud, 10-bit Mode, REFCLK = 2x Character Rate REFCLK Clock Frequency--50 to 100 MBaud, 8-bit Mode, REFCLK = 2x Character Rate REFCLK Clock Frequency--50 to 100 MBaud, 10-bit Mode, REFCLK = 4x Character Rate REFCLK Clock Frequency--50 to 100 MBaud, 8-bit Mode, REFCLK = 4x Character Rate REFCLK Clock Frequency--100 to 200 MBaud, 10-bit Mode, REFCLK = Character Rate REFCLK Clock Frequency--100 to 200 MBaud, 8-bit Mode, REFCLK = Character Rate REFCLK Clock Frequency--100 to 200 MBaud, 10-bit Mode, REFCLK = 2x Character Rate REFCLK Clock Frequency--100 to 200 MBaud, 8-bit Mode, REFCLK = 2x Character Rate tREFCLK tREFH tREFL tREFRX REFCLK Period REFCLK HIGH Time REFCLK LOW Time REFCLK Frequency Referenced to Received Clock Period
[19]
CY7C9689
SPDSEL 0 0 0 0 1 1 1 1
RANGESEL 0 0 1[18] 1[18] 0 0 1 1
BYTE8/ 10 0 1 0 1 0 1 0 1
Min. 8.33 10 16.67 20 20 10 16.67 8.33 25 6.5 6.5 -0.04
Max 16.67 20 33.3 40 40 20 33.3 16.67 120
Unit MHz MHz MHz MHz MHz MHz MHz MHz ns ns ns
+0.04
%
CY7C9689 PECL Input/Output Switching Characteristics Over the Operating Range
Parameter tB tSA tEFW tRISE tFALL tDJ tRJ tJT Bit Time Static Alignment
[14, 23] [14, 20, 24] [14]
Description
Min. 20.0 TBD 0.75 200 200
Max 5.0 TBD
Unit ns ps UI
Error Free Window
PECL Output Rise Time 20-80% (PECL Test Load) PECL Output Fall Time 80-20% (PECL Test Load) Deterministic Jitter (peak-peak) Random Jitter ()
[14, 26] [14] [14, 25]
1700 1700 TBD TBD TBD
ps ps ps ps ps
[14]
Transmitter Total Output Jitter (peak-peak)
Notes: 18. When configured for synchronous operation with the FIFOs bypassed (FIFOBYP is LOW), if RANGESEL is HIGH the SPDSEL input is ignored and operation is forced to the 100-200 MBaud range 19. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be within 0.04% of the transmitter PLL reference (REFCLK) frequency, necessitating a 200-PPM crystal. 20. Receiver UI (Unit Interval) is calculated as (1/f REF) if no data is being received, or (1/f REF) of the remote transmitter if data is being received. In an operating link this is equivalent to 10 * tB. 21. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads. 22. The PECL switching threshold is the midpoint between the PECL- VOH, and VOL specification (approximately VDD - 1.33V). 23. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in 3,000 nominal transitions until a character error occurs. 24. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured over the operating range, input jitter < 50% Dj. 25. While sending continuous JK, outputs loaded to 50 to VDD-1.3V, over the operating range. 26. While sending continuous HH, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range.
20
PRELIMINARY
CY7C9689 HOTLink Transmitter Switching Waveforms
Write Cycle Asynchronous (FIFO) Interface EXTFIFO=HIGH FIFOBYP=HIGH
TXCLK
CY7C9689
tTXCLK tTXCPWH t TXCPWL
tTXDS
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN Note 27
tTXDH
tTXENH
NO OPERATION
tTXENS
tTXA TXFULL TXHALF TXEMPTY tTXA
Write Cycle Asynchronous (FIFO) Interface EXTFIFO=LOW FIFOBYP=HIGH
TXCLK
tTXDS
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] Note 28
tTXDH
tTXENS
TXEN
t TXENH
NO OPERATION
tTXA TXFULL TXHALF TXEMPTY
t TXA
Notes: 27. When EXTFIFO is HIGH, the write data is captured on the clock cycle following TXEN = HIGH. 28. When EXTFIFO is LOW, the write data is captured on the same clock cycle as the TXEN=LOW.
21
PRELIMINARY
CY7C9689 HOTLink Transmitter Switching Waveforms (continued)
OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO=HIGH FIFOBYP=HIGH
TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
CY7C9689
NO OPERATION
Note 29 t TXRSS tTXRSH
TXRST
t TXCES
CE
t TXCEH
tTXOE
TXFULL TXHALF TXEMPTY
tTXOAZ
tTXOZA OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO=LOW FIFOBYP=HIGH
TXCLK TXHALT TXSC/D TXDATA[7:0] XDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
NO OPERATION
tTXRSS
CE TXRST CE TXRST
tTXRSH
Note 29 tTXCES tTXCEH
tTXOE
TXFULL TXHALF TXEMPTY
tTXOAZ
tTXOZA
Note: 29. Illustrates timing only. TXEN and TXRST not usually active in same time period.
22
PRELIMINARY
CY7C9689 HOTLink Transmitter Switching Waveforms (continued)
Write Cycle Synchronous Interface EXTFIFO=HIGH FIFOBYP=LOW
REFCLK
CY7C9689
tREFCLK tREFH t REFL
tREFDS
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN Note 30
tREFDH
tREFENH
NO OPERATION
tREFENS t
TXFULL TXHALF TXEMPTY
TRA
t
TRA
Write Cycle Synchronous Interface EXTFIFO=LOW FIFOBYP=LOW
REFCLK
t REFDS
TXHALT TXSC/D TXDATA[7:0] DATA[9:8]/TXCMD[2:3] TXCMD[1:0] Note 31
tREFDH
tREFENS
TXEN
t REFENH
NO OPERATION
TXFULL TXHALF TXEMPTY
Notes: 30. When transferring data to the Transmitter input from a depth expanded external FIFO, the data is captured from the external FIFO one clock cycle following the actual enable (TXEN = HIGH). 31. When transferring data to the Transmitter input from a synchronous external controller, the data is captured in the same clock cycle as the actual enable (TXEN = LOW).
23
PRELIMINARY
CY7C9689 HOTLink Transmitter Switching Waveforms (continued)
OUTPUT ENABLE Timing Synchronous Interface EXTFIFO=HIGH FIFOBYP=LOW
CY7C9689
REFCLK
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
tREFENH
NO OPERATION
tREFENS tREFCES
CE
t REFCEH
tREFOE
TXFULL TXEMPTY
tREFAZ
tREFZA OUTPUT ENABLE Timing Synchronous Interface EXTFIFO=LOW FIFOBYP=LOW
REFCLK
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
NO OPERATION
CE
TXFULL TXEMPTY
24
PRELIMINARY
CY7C9689 HOTLink Receiver Switching Waveforms
Read Cycle Asynchronous (FIFO) Interface EXTFIFO=HIGH FIFOBYP=HIGH tRXCLKOD tRXCPWH
RXCLK
CY7C9689
tRXCLKOP tRXCLKIP tRXCLKOD tRXCPWL
tRXENS
RXEN
READ
tRXENH
NO OPERATION READ
tRXA
RXEMPTY Note 32
FIFO EMPTY
tRXA
LFI RXFULL RXHALF RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0] CE
VALID DATA
Note 33
Read Cycle Asynchronous (FIFO) Interface EXTFIFO=LOW FIFOBYP=HIGH
RXCLK
tRXENS
RXEN
READ
tRXENH
tRXA
RXEMPTY LFI RXFULL RXHALF RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0] CE
tRXA
FIFO EMPTY
VALID DATA
Note 34
Notes: 32. When transferring data from the Receive FIFO to a depth expanded external FIFO, the data is sent to the external FIFO on the same clock cycle that RXEN=HIGH. RXEMPTY=LOW indicates that data is available. 33. On inhibited reads, or if the Receive FIFO goes empty, the data outputs do not change. 34. When reading data from synchronous data interface, the data is captured on any clock cycle that RXEN=LOW. RXEMPTY=HIGH indicates data is available. RXEMPTY=LOW indicates that the FIFO is empty.
25
PRELIMINARY
CY7C9689 HOTLink Receiver Switching Waveforms (continued)
Output Enable Timing
CY7C9689
RXCLK
tRXENS
RXEN
tRXENH
NO OPERATION
Note 35
RXRST
tRXRSH
tRXRSS
tRXCES
CE
tRXCEH
LFI RXFULL RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0]
tRXOE
OLD DATA
tRXAZ
Note 36
tRXZA
tREFCLK tREFL tREFH
REFCLK
Static Alignment
tB/2- tSA tB/2- tSA
Error-Free Window
tEFW INA INB tB SAMPLE WINDOW BIT CENTER BIT CENTER
INA INB
Notes: 35. Illustrates timing only. RXEN and RXRST not usually active in same time period. 36. Receive FIFO Reads are inhibited while the outputs are High-Z.
26
PRELIMINARY
Table 3. HOTLink TAXI Compatible Encoder Patterns 4B/5B Encoder HEX Data 0 1 2 3 4 5 6 7 8 9 A B C D E F 4-bit Binary Data[37] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 5-bit Encoded Symbol[38,39] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 HEX Data 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 5B/6B Encoder 5-bit Binary Data[37] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 10001 11001 11010 11011 11100 11101 11110 11111
CY7C9689
6-bit Encoded Symbol[38,39] 110110 010001 100100 100101 010010 010011 010110 010111 100010 110001 110111 100111 110010 110011 110100 110101 111110 011001 101001 101101 011010 011011 011110 011111 101010 101011 101110 101111 111010 111011 111100 111101
Notes: 37. Binary Input Data is the parallel input data which is input to the Transmitter and output from the Receiver. Binary bits are listed from left to right in the following order: 8-Bit mode (BYTE8/10 is HIGH and TXSC/D or RXSC/D is LOW)--TXDATA/RXDATA[7], [6], [5], [4], and TXDATA/RXDATA[3], [2], [1], [0]. 10-Bit mode (BYTE8/10 is LOW and TXSC/D or RXSC/D is LOW)--TXDATA/RXDATA[8], [7], [6], [5], [4], and TXDATA/RXDATA[9], [3], [2], [1], [0]. 38. The ENCODED Symbols are shown here as "ones and zeros", but are converted to and from an NRZI stream at the transmitter output and receiver input. NRZI represents a "one" as a state transition (either LOW-to-HIGH or HIGH-to-LOW) and a "zero" as no transition within the bit interval. 39. Encoded Serial Symbol bits are shifted out with the most significant bit (Left-most) of the most significant nibble coming out first.
27
PRELIMINARY
Table 4. HOTLink TAXI Compatible Command Symbols CY7C9689 (Transmitter) Command Input TXCMD[3:0] HEX 0 1 2 3 4 5 6 7 8
[41]
CY7C9689
CY7C9689 (Receiver) Command Output RXCMD[3:0]
Binary CMD[40] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00 01 10 11
Encoded Symbol[38, 39] 11000 10001 11111 11111 01101 01101 01101 11001 11111 00100 01101 00111 11001 00111 11001 11001 00100 00100 00100 11111 00100 00000 00111 00111 00111 11001 00000 00100 00000 11111 00000 00000 011000 100011 111111 111111 011101 011101 011101 111001
Mnemonic JK (8-bit SYNC) II TT TS IH TR SR SS HH HI HQ RR RS QH QI QQ LM (10-bit SYNC) I'I' T'T' T'S'
HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3
Binary CMD[40] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00 01 10 11
8-bit mode (BYTE8/10 is HIGH)
9[41] A[41] B C D[41] E
[41]
F[41] 0 1 2 3
10-bit mode (BYTE8/10 is LOW)
Notes: 40. Binary CMD is the parallel input data which is input to the Transmitter and output from the Receiver. Binary bits are listed from left to right in the following order: 8-Bit mode (BYTE8/10 is HIGH and TXSC/D or RXSC/D is HIGH)--TXCMD/RXCMD[3], [2], [1], [0]. 10-Bit mode (BYTE8/10 is LOW and TXSC/D or RXSC/D is HIGH)--TXCMD/RXCMD[1], [0]. 41. While these Commands are legal data and will not disrupt normal operation if used occasionally, they may cause data errors if grouped into recurrent fields. Normal PLL operation cannot be guaranteed if one or more of these commands is continuously repeated.
Functional Description
Transmit FIFO Reset Sequence On power-up, the Transmitter and Receiver FIFOs may contain random data. The Transmitter FIFO will empty automatically as the Transmitter sends the random data (assuming that TXHALT is not LOW) within the first 256 character-times after power is applied. The Receiver FIFO will retain any random data stored in it at power-up, and will accumulate all the random data being received from any attached transmitter as it is powered up. This random received data can be "flushed" by reading it, or the Receive FIFO can be "reset" to remove the unwanted data. The Transmit FIFO reset sequence (see Figure 2) is started when TXRST and CE are first sampled LOW by the rising edge of TXCLK. Because a Tx_RstMatch condition is present, the Transmit FIFO flags are asserted and can be used to track the status of any Transmit FIFO reset in progress. Once the reset 28
sequence has reached its maximum count (seven TXCLK cycles), the Transmit FIFO flags are asserted to indicate a FULL condition (TXEMPTY is deasserted, and both TXHALF and TXFULL are asserted). This indicates that the Transmit FIFO reset has been recognized by the Transmit Control State Machine and that a reset has been started. However, if the TXEN is asserted prior to or during the assertion and sampling of TXRST, the reset sequence is inhibited until TXEN is removed. NOTE: The FIFO FULL state forced by the reset operation is different from a FULL state caused by normal FIFO data writes. For normal FIFO write operations, when FULL is first asserted, the Transmit FIFO must still accept up to four additional writes of data. When a FULL state is asserted due to a Transmit FIFO reset operation, the FIFO will not accept any additional data. The Transmit FIFO reset does not complete until the external reset condition is removed. This can be removed by deassertion of either TXRST or CE. If CE is deasserted (HIGH) to
PRELIMINARY
CY7C9689
TXCLK
TXRST
TXEN
Note 42
CE
[43]
Tx_RstMatch
Tx_Match
[43]
Tx_FIFO_Reset
[43]
TXFULL
Note 42
Not Full
Full
Figure 2. Transmit FIFO Reset Sequence remove the reset condition, the Transmit FIFO flag's drivers are disabled, and the Transmit FIFO must be addressed at a later time to validate completion of the Transmit FIFO reset. If TXRST is deasserted (HIGH) to remove the reset condition, the Tx_RstMatch is changed to a Tx_Match, and the Transmit FIFO status flags remain driven. The Transmit FIFO reset operation is complete when the Transmit FIFO flags indicate an EMPTY state (TXEMPTY is asserted and both TXHALF and TXFULL are deasserted). A valid Transmit FIFO reset sequence is shown in Figure 2. Here the TXRST and CE are asserted (LOW) at the same time. When these signals are both sampled LOW by TXCLK, a Tx_RstMatch condition is present. With TXEN deasserted (HIGH), the Transmit FIFO is not selected for data transfers. This Tx_RstMatch condition must remain for seven TXCLK cycles to initiate the Tx_FIFO_Reset. Following this the TXFULL FIFO status flag is asserted to indicate that the Transmit FIFO reset sequence has completed and that a Transmit FIFO reset is in progress. When the TXRST signal is deasserted (HIGH), CE remains LOW to allow the FIFO status flags to be driven. This allows the completion of the reset operation to be monitored. To allow better multi-tasking on multi-PHY implementations, it is possible to deassert CE (HIGH) as soon as the FULL state is indicated. The FIFO reset operation will complete and the EMPTY state (indicating completion of the reset operation) can be detected during a separate polling operation. For those links implemented with a single PHY, it is possible to hardwire CE LOW and still perform normal accesses and reset
Notes: 42. Signals shown as dotted lines indicate timing and levels when configured for external FIFOs (EXTFIFO is HIGH). 43. Signal names listed in italics are internal signals, shown for reference only.
operations. This is shown in Figure 3. In a single-PHY implementation, a Transmit FIFO reset can never be initiated with TXEN asserted at the same time as TXRST. Since CE is always LOW, any assertion of TXEN causes the Transmit FIFO to be selected, clearing the reset counter. Figure 4 shows a sequence of input signals which will not produce a FIFO reset. In this case TXEN was asserted to select a Transmit FIFO for data transfers. Because TXEN remains active, the assertion of CE and TXRST does not initiate a reset operation. This is shown by the TXFULL flag remaining HIGH (deasserted) following what would be the normal expiration of the seven-state reset counter. Receive FIFO Reset Sequence The Receive FIFO reset sequence operates (for the most part) the same as the Transmit FIFO reset sequence. The same requirements exist for the assertion state of RXRST and selection of the interface. A sample Receive FIFO reset sequence is shown in Figure 5. Upon recognition of a Receive FIFO reset, the Receive FIFO flags are forced to indicate an EMPTY state to prohibit additional reads from the FIFO. Unlike the Transmit FIFO, where the internal completion of the reset operation is shown by first going FULL and later going EMPTY when the internal reset is complete, there is no secondary indication of the completion of the internal reset of the Receive FIFO. The Receive FIFO is usable as soon as new data is placed into it by the Receive Control State Machine.
29
PRELIMINARY
CY7C9689
TXCLK
TXRST
TXEN CE
[43]
Note 42
Tx_RstMatch
[43]
Tx_Match
[43]
Tx_FIFO_Reset
TXFULL
Note 42
Not Full
Full
Figure 3. Transmit FIFO Reset Sequence with Constant CE
TXCLK
TXRST
Note 42
TXEN
CE
[43]
Tx_RstMatch
Tx_Match
[43]
Tx_FIFO_Reset
[43]
TXFULL
Note 42
Not Full
Figure 4. Invalid Transmit FIFO Reset Sequence with TXEN Asserted
30
PRELIMINARY
CY7C9689
RXCLK
RXRST
RXEN
Note 42
CE
[43]
Rx_RstMatch
Rx_Match
[43]
Rx_FIFO_Reset
[43]
RXEMPTY
Note 42
Not Empty
Empty
Figure 5. Receive FIFO Reset Sequence
31
PRELIMINARY
Printed Circuit Board Layout Suggestions
CY7C9689
Power Supply Bypass 0.01-F MLC X7R 1206 Chip Cap (4 sites)
INA+
OUTA+ OUTB+ INB+
Power Supply Bypass 0.01-F MLC X7R CURSETB Resistor
CURSETA Resistor
Power Supply Bypass 0.01-F MLC X7R 1206 Chip Cap (2 sites) RXSC/D REFCLK
CY7C9689-AC CY7C9689-AC
Power Supply Bypass 0.01-F MLC X7R RESET
Via to V DD plane Via to VSS plane
Power Supply Bypass 0.01-F MLC X7R
This is a typical printed circuit board layout showing example placement of power supply bypass components and other components mounted on the same side as the CY7C9689.
Other layouts, including cases with components mounted on the reverse side would work as well.
32
PRELIMINARY
Ordering Information
Ordering Code CY7C9689-AC CY7C9689-AI Package Name A100 A100 Package Type 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack
CY7C9689
Operating Range Commercial Industrial
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
HOTLink is a trademark of Cypress Semiconductor, Inc. AMD, TAXI, and TAXIchip are trademarks of Advanced Micro Devices. Inc.
(c)Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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